Pilot line on advanced Fully Depleted Silicon On Insulator technologies targeting 7nm

The proposed pilot line shall work at all levels of the main technological steps:

• Development of the 10nm to 7nm FD-SOI technology modules for enhancing the performances of the current FD-SOI technology, including RF applications, through reducing the transistor size. The main technologies to be developed shall be: the enhancement of the carrier mobility, the optimization of the transistor process, the development of the Middle-of-Line (MoL) modules and the development of Back-End-of-Line (BEOL) process modules. They should be performed through a strong interaction between the process and design teams in order to optimize the FD-SOI device performances, and to deliver the PDKs for each developed technology and process modules.

• Development of the additional process modules.

o Memories: The Pilot Line platform should be enhanced by adding in the metal interconnections. These additions can offer new ranges of applications and would allow breakthroughs like in-memory computing. Several memory NVM options (PCRAM, FeRAM, OxRAM, MRAM etc.) will have to be proposed to the pilot line partners, by themselves or in collaboration with other pilot lines.

o 3D options: The Pilot Line should offer design environments compatible with new 3D architectures, chip-on-wafer and wafer-to-wafer alignment technologies and efficient bonding techniques. 3D option based on monolithic sequential integration should also be proposed to further improved performances and decreased cost.

• Delivery of updated PDKs

▪ Once the technology and additional process module will be mature enough, the proposed pilot line will have to continuously deliver updated PDKs of the developed technologies for technology assessment.

▪ Any stakeholder must have access to the PDKs, describing the updated 10-7nm FD-SOI technology and the additional modules through the Design Platforms, the Competence Centers and/or directly to the pilot line.

• Realization of circuits through Multi-Project-Wafers (MPW) runs for European partners, according to an operational and access policy defined for the pilot line for the collaboration with those stakeholders.

The access policy from the different stakeholders to the pilot line should be defined in the proposal according to fair and non-discriminatory principles.

During the whole duration of the pilot line, the hosting entity and other partners should provide training to any European partner interested in designing devices based on FD-SOI technology in order to use the full benefits of this technology, as well as for students for up- and re-skilling in order to attract new talents in the European semiconductor industry.

Collaborations: The proposed FD-SOI pilot line must facilitate the collaboration with other pilot lines, with design platforms and competence centres to allow contributions from other stakeholders that develop a strong expertise in a specific domain related to the topics of this pilot line.